`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Westlake University
// Engineer: shenziyang@westlake.edu.cn
// 
// Create Date: 2021/11/20 21:32:28
// Design Name: HW2
// Module Name: tb_BCD_dec_adder1bit
// Project Name: hw2
// Target Devices: VCU118
// Tool Versions: vivado 2020.1
// Description: testbench for 1 bit adder
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module tb_BCD_dec_adder1bit;
    reg cin;
    reg clk;
    wire cout;
    wire D;
    wire C;
    wire B;
    wire A;
    always begin                    //clock generation
        #5 clk = 1; #5 clk = 0;
    end
    initial begin                   //initialization
        cin <= 1;
        #10 cin <= 0;
        #110 $finish;
    end

BCD_dec_adder1bit inst_BCD_dec_adder1bit(cin, clk, cout, D, C, B, A);
endmodule
